NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device

ABSTRACT

In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/263,716, filed on Nov. 1, 2005, which relies for priority upon KoreanPatent Application No. 10-2005-0023751 filed on Mar. 22, 2005, thecontents of which are herein incorporated by reference in theirentirety.

BACKGROUND OF THE INVENTION

The present invention is concerned with semiconductor memory devices,and, in particular, relates to a NOR flash memory device and method ofserially sensing a data bit.

Semiconductor memory devices are data storage apparatuses capable ofstoring and retrieving. Such devices can be classified generally asrandom access memories (RAMs) and read only memories (ROMs). The RAMdevices are volatile memory devices that lose their data when the powersupply is cut off or interrupted, while the ROM devices are nonvolatilememory devices that are configured to retain their data even withoutpower supply. The RAM devices include dynamic RAMs (DRAMs), static RAMs(SRAMs), and so forth, while the ROMs include programmable ROMs (PROMs),erasable PROMs (EPROMs), electrically EPROMs (EEPROMs), flash memories,and so forth.

Flash memory devices are attractive because they consume relatively lowpower and are flexible and efficient in inputting and outputtinginformation. For these reasons, they are especially applicable to beemployed in portable apparatuses such as digital cameras, mobile phones,PDAs, and the like. Flash memory devices can be generally categorizedinto NAND and NOR types in accordance with the structural feature of thememory cell array. The NAND flash memory devices are relatively simplein structure, so they are advantageous in enlarging the device storagecapacity and cheaper than the NOR type devices. The NAND flash memorydevices are commonly utilized as data storage components for USB storageapparatuses or MP3 players. Otherwise, the NOR flash memory devices areoperable in high speed devices as code storage components, being usuallyembedded in mobile telephone terminals that require high-rate operation.

A memory cell of the NOR flash memory device is formed by having sourceand drain regions doped with N+ impurities, between which a channelregion is interposed in a P-type semiconductor substrate. The memorycell also includes a floating gate formed by interposing a thininsulation film under 100 Å on the channel region, and a control gateformed by interposing an insulation film on the floating gate. Thesource, the drain, the control gate, and the substrate, of the memorycell, are connected to bias voltages during programming, erasing, orreading operations.

For instance, in a reading operation, a selected memory cell to be readout is supplied with about 1V to the drain region, 4.5V to the controlgate, 0V to the source region, and 0V to the substrate. When the readingoperation is carried out in the bias condition, a programmed cell doesnot flow a current from the drain region to the source region, and anerased cell flows a current from the drain region to the source regionthrough the channel. Here, the programmed cell is referred to as‘OFF-cell’, while the erased cell is referred to as ‘ON-cell’.

On the other hand, it is preferred that the NOR flash memory device havea larger storage capacity in a smaller area. In implementing thesmall-area large-capacity NOR flash memory device, it is necessary toenhance the integration density, but there are inherent limits to makingthe integration density higher under present semiconductor processingtechnology. Thus, studies for methodologies to overcome the limit onprocessing technology have been conducted to increase the storagecapacity even without raising the integration density. One of themethods is storing multiple bits of data in a single memory cell. Amemory cell storing multiple data bits is referred to as a multilevelcell (MLC). For example, a memory cell storing 2-bit data contains 4state levels such as ‘11’, ‘10’, ‘01’, and ‘00’. The 4 state levels aredifferentiated by differences in the levels of current that flow throughthe memory cell during a reading operation.

In order to sense or detect multiple data bits stored in the multilevelcell, a sense amplifier and a data buffer are used, as well known inthis art. The sense amplifier finds multiple data bits stored in themultilevel cell by detecting and amplifying a difference between areference current amount and a current amount flowing through themultilevel cell. The data buffer buffers data detected and output fromthe sense amplifier. The buffered data is stored in a data latch througha data line.

In general, a NOR flash memory device uses serial and parallel sensingtechniques in order to detect multiple data bits stored in a multilevelcell. The serial sensing technique is a way of detecting multiple databits in sequence by means of a single amplifier, while the parallelsensing scheme is a way of detecting multiple data bits at a time bymeans of plural amplifiers. As the parallel sensing scheme employs amultiplicity of sense amplifiers, sensing speed is faster but a sensingmargin is degraded due to mismatches between different sense amplifiers.

Otherwise, the serial sensing scheme is more advantageous than theparallel sensing scheme in overcoming the problem of mismatches becauseit uses a single sense amplifier. However, as the serial sensing schemedetects multiple data bits in sequence by means of a single amplifier, adata line may be influenced by a data bit generated from the previoussensing step. Further, the condition of the data line frequently changesfrom a high level to a low level or from a low level to a high level,resulting in a decrease of sensing margin in accordance with variationof state levels.

SUMMARY OF THE INVENTION

The present invention addresses the aforementioned limitations,providing a NOR flash memory device operable with a data lineconditioned in a uniform level without being affected by the state ofthe previous data bit by initializing the data line whenever sensingeach of multiple data bits.

In one aspect, the present invention is directed to a NOR flash memorydevice comprising a multilevel cell, a sense amplifying circuit, a databuffer, a data latch circuit, and a control logic circuit. The senseamplifying circuit serially detects the multiple data bits stored in themultilevel cell. The data buffer buffers a data bit detected by thesense amplifying circuit. The data latch circuit holds an output valueof the data buffer. The control logic circuit regulates the senseamplifying circuit to detect a lower data bit stored in the multilevelcell in response to a higher data bit held in the data latch circuit.The control logic circuit initializes an output terminal of the databuffer before detecting each of the multiple data bits by the senseamplifying circuit.

In one embodiment, the control logic circuit provides a buffer enablingsignal to the data buffer to buffer the data bit detected by the senseamplifying circuit. The data buffer comprises: a tri-state buffersequentially buffering each of the multiple data bits detected by thesense amplifying circuit, in response to the buffer enabling signal; andan initializing circuit initializing an output node of the tri-statebuffer before detecting each of the multiple data bits by the senseamplifying circuit, in response to a reset signal provided by thecontrol logic circuit. The tri-state buffer is an inverter operating inresponse to the buffer enabling signal and the initializing circuit is aMOS transistor forming a current channel between the output node of thetri-state buffer and a ground voltage terminal in response to the resetsignal.

In another aspect, the present invention is directed to a NOR flashmemory device comprising a multilevel cell, a sense amplifying circuit,a data buffer, a data latch circuit, and a control logic circuit. Thesense amplifying circuit serially detects the multiple data bits storedin the multilevel cell. The data buffer buffers a data bit detected bythe sense amplifying circuit. The data latch circuit stores an outputvalue of the data buffer. The control logic circuit regulates the senseamplifying circuit to detect a lower data bit stored in the multilevelcell in response to a higher data bit held in the data latch circuit.The control logic circuit initializes an output terminal of the databuffer while detecting each of the multiple data bits by the senseamplifying circuit.

In one embodiment, the control logic circuit initializes the outputterminal of the data buffer when the sense amplifying circuit beginsdetecting each of the multiple data bits.

In another embodiment, the control logic circuit provides a bufferenabling signal to the data buffer to buffer the data bit detected bythe sense amplifying circuit. The data buffer comprises: a tri-statebuffer sequentially buffering each of the multiple data bits detected bythe sense amplifying circuit, in response to the buffer enabling signal;and an initializing circuit initializing an output node of the tri-statebuffer while detecting each of the multiple data bits by the senseamplifying circuit, in response to a reset signal provided by thecontrol logic circuit. The tri-state buffer is an inverter operating inresponse to the buffer enabling signal and the initializing circuit is aMOS transistor forming a current channel between the output node of thetri-state buffer and a ground voltage terminal in response to the resetsignal.

In another aspect, the present invention is directed to a method ofsequentially sensing multiple data bits stored in a multilevel cell of aNOR flash memory device comprising the steps of: initializing a dataline and sensing a higher data bit; loading the sensed higher data biton the data line and latching the loaded higher data bit; initializingthe data line and sensing a lower data bit in response to the latchedhigher data bit; and loading the sensed lower data bit on the data lineand latching the loaded lower data bit.

In one embodiment of the method, the data line is initialized beforesensing the higher data bit and also initialized before sensing thelower data bit.

In another embodiment of the method, the data line is initialized whilesensing the higher data bit and also initialized while sensing the lowerdata bit, for example when beginning to sense the higher data bit andwhen beginning to sense the lower data bit.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description ofpreferred embodiments of the invention, as illustrated in theaccompanying drawings in which like reference characters refer to thesame parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention. In the drawings:

FIG. 1 is a block diagram illustrating a NOR flash memory deviceaccording to a preferred embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating the NOR flash memory deviceshown in FIG. 1 in detail;

FIG. 3 is a timing diagram illustrating the state of various signalsduring a serial sensing operation to initialize a data line before asensing operation in the NOR flash memory device illustrated in FIG. 2;and

FIG. 4 is a timing diagram illustrating the state of various signalsduring a serial sensing operation to initialize a data line during asensing operation in the NOR flash memory device illustrated in FIG. 2.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Preferred embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstructed as limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete. Like numerals refer to like elements throughout thespecification.

FIG. 1 is a block diagram illustrating a NOR flash memory deviceaccording to a preferred embodiment of the present invention. Referringto FIG. 1, the NOR flash memory device 100 is comprised of a multilevelcell (MLC) 110, a sense amplifying circuit 120, a data buffer 130, adata latch circuit 140, and a control logic circuit 150. The NOR flashmemory device 100 sequentially reads out multiple data bits stored inthe multilevel cell 110.

The multilevel cell 110 stores multiple data bits. As an example,assuming that the multilevel cell 110 stores 2-bit data of ‘10’, ‘1’ isa higher data bit and ‘0’ is a lower data bit. Here, the higher data bitis a relative meaning as being detected earlier than the lower data bit.In other words, in 3-bit data of ‘abc’, ‘a’ is a higher data bit sensedearlier than ‘b’ while ‘b’ is a higher data bit sensed earlier than ‘c’.

The sense amplifying circuit performs a serial sensing operation. Theserial sensing operation operates to sense a lower data bit afterreading out a higher data bit by means of a single sense amplifier. Thedata buffer 130 buffers a data bit detected by the sense amplifyingcircuit 120. The data latch circuit 140 is connected to the data buffer130 through a data line dl, latching an output value of the data buffer130.

The control logic circuit 150 regulates the sense amplifying circuit 120to detect a higher data bit stored in the multilevel cell 110. The senseamplifying circuit 120 detects the higher data bit under control by thecontrol logic circuit 150. During this operation, the control logiccircuit 150 initializes an output terminal (or a data line DL) of thedata buffer 130 before detecting, or while detecting, the higher databit by the sense amplifying circuit 120. The data buffer 130 buffers thehigher data bit detected by the sense amplifying circuit 120 aftercompleting the initialization for the output terminal of the data buffer130. The data latch circuit 140 holds the higher data bit buffered bythe data buffer 130.

Next, the control logic circuit 150 regulates the sense amplifyingcircuit 120 to detect a higher data bit stored in the multilevel cell110 in response to the higher data bit MSB_D held in the data latchcircuit 140. The sense amplifying circuit 120 detects a lower data bitunder the control of the control logic circuit 150. During this, thecontrol logic circuit 150 initializes the output terminal of the databuffer 130 before detecting, or while detecting, the lower data bit bythe sense amplifying circuit 120. The data buffer 130 buffers the lowerdata bit detected by the sense amplifying circuit 120 after completingthe initialization for the output terminal of the data buffer 130. Andthen, the data latch circuit 140 holds the lower data bit buffered bythe data buffer 130.

The NOR flash memory device 100 outputs multiple data bits, which aretemporarily stored in the data latch circuit 140, to the external systemthrough a data output circuit (not shown).

The NOR flash memory device 100 according to the present inventioninitializes an output terminal of the data buffer 130 before, or while,the sense amplifying circuit 120 detects each of the multiple data bitsstored in the multilevel cell 110. Thus, it is possible to conduct astabilized serial sensing operation in a uniform level regardless of theprevious state of the data line DL. Further, as the serial sensingoperation in the NOR flash memory device according to the presentinvention is able to normally conduct sensing operations with a leveluniformity, it is possible to assure a larger sensing margin than theconventional approach and to enhance sensing speed.

FIG. 2 is a circuit diagram illustrating an internal structure of theNOR flash memory device shown in FIG. 1 in detail. Referring to FIG. 2,as aforementioned, the NOR flash memory 100 is composed of themultilevel cell (MLC) 110, the sense amplifying circuit 120, the databuffer 130, the data latch circuit 140, and the control logic circuit150. The control logic circuit 150 is comprised of a reference voltagegenerator 151, a switching circuit 152, a reference voltage selector153, and a controller 154.

The multilevel cell 110 is able to store multiple data bits therein. Forexample, the multilevel cell 110 is capable of storing 2-bit data suchas ‘11’, ‘10’, ‘01’or ‘00’, or 3-bit data such as ‘111’, ‘110’, . . . ,‘001’or ‘000’, in accordance with a state of threshold voltage thereof.

The sense amplifying circuit 120 detects and amplifies a differencebetween a reference current and a current flowing through the multilevelcell 110. The sense amplifying circuit 120 is comprised of a bitlineprecharging circuit 121, a bitline discharging circuit 122, a bitlinebiasing circuit 123, and an amplifier 124.

The bitline precharging circuit 121 is composed of a PMOS transistorP21, supplying a power source voltage to the sense amplifying circuit120 in response to a bitline precharging signal BLPRE. The bitlinedischarging circuit 122 is composed of an NMOS transistor N22,exhausting charge that is accumulated in a corresponding bitline beforesensing multiple data bits stored in the multilevel cell 110. Thebitline discharging circuit 122 activates a discharging operation inresponse to a bitline discharging signal BLDIS. During this, an outputnode of the bitline precharging circuit 121 is set on high level. Thebitline biasing circuit 123 is composed of an NMOS transistor N21, beingsupplied with a DC voltage of a predetermined level (e.g., 1.5V) duringa read operation. Between the bitline precharging circuit 121 and thebitline biasing circuit 123, a PMOS transistor P22 is disposed to form acurrent mirror. The amplifier 124 enlarges a difference between areference current and a current flowing through the multilevel cell 110,sensing (or detecting) multiple data bits stored in the multilevel cell110.

The sense amplifying circuit 120 utilizes the single amplifier 124 indetecting multiple data bits stored in the multilevel cell 110. Thesense amplifying circuit 110 detects 2-bit data by way of performing twosensing operations using the single amplifier 124, which is referred toas a serial sensing operation. In contrast, an operation that senses2-bit data at the same time by means of plural amplifiers is referred toas a parallel sensing operation. As mentioned above, a serial sensingoperation is able to overcome the problem of amplifier mismatchassociated with the parallel sensing operation.

The data buffer 130 sequentially buffers multiple data bits, which aredetected by the sense amplifying circuit 120, each bit by each bit. Thedata buffer 130 includes a tri-state buffer 131 and an initializingcircuit 132.

The tri-state buffer 131 is comprised of an inverter that inverts anoutput value of the sense amplifying circuit 120, and a switch that isturned on or off in response to buffer enabling signals ENBF and nENBF.The inverter is constructed of a PMOS transistor P31 and a NMOStransistor N31. The PMOS transistor P31 is constructed of a sourceconnected to the power source voltage and a gate coupled to the outputterminal SAO of the sense amplifying circuit 120. The NMOS transistorN31 is constructed of a source connected to the ground voltage and agate coupled to the output terminal SAO of the sense amplifying circuit120. The switch is serially connected between the PMOS and NMOStransistors P31 and N31, being constructed of PMOS and NMOS transistorsP32 and N32 turned on or off in response to the buffer enabling signalsENBF and nENBF. Here, the buffer enabling signals ENBF and nENBF arecomplementary to each other.

The initializing circuit 132 is connected to the output terminal of thedata buffer 130, i.e., the data line DL, to which the PMOS and NMOStransistors P32 and N32 are connected in common. The initializingcircuit 132 initializes the output terminal DL of the tri-state buffer131 in response to a reset signal PRST. Referring to FIG. 2, theinitializing circuit 132 is composed of an NMOS transistor N33 forming acurrent channel between the output node of the tri-state buffer 131 andthe ground voltage terminal in response to the reset signal PRST.

The data latch circuit 140 is connected to the data buffer by way of thedata line DL. The data latch circuit 140 holds an output value of thedata buffer 130 for a time period.

Continuing to refer to FIG. 2, the reference voltage generator 151outputs reference voltages DG_M, DG_L, and DG_H having three differentvoltages from each other. The first reference voltage DG_M is providedto output a higher data bit, while the second voltage DG_L or the thirdreference voltage DG_H is provided to output a lower data bit.

The switching circuit 152 is composed of switches S1, S2, and S3providing one of the first through third reference voltages to apositive (+) terminal of the amplifier 124 in response to selectionsignals MSB_M, LSB_L, and LSB_H. Here, the switch S1, S2, or S3 may beconstructed of a pass transistor, a PMOS transistor, or an NMOStransistor. When the first selection signal MSB_M is input to theswitching circuit 152, the sense amplifying circuit 120 detects a higherdata bit. Next, if the second or third selection signal LSB_L or LSB_His applied to the switching circuit 152, the sense amplifying circuit120 detects a lower data bit.

The reference voltage selection circuit 153 generates the firstselection signal MSB_M to operate the sensing operation for a higherdata bit in response to a higher-bit enabling signal ENMSB. The firstselection signal MSB_M is applied to the second switch S2 of theswitching circuit 152. During this, the sense amplifying circuit 120detects a higher data bit, and the higher data bit detected is held inthe data latch circuit 140 after passing through the data buffer 130.Next, the reference voltage selection circuit 153 receives the higherdata bit MSB_D from the data latch circuit 140. The reference voltageselection circuit 153 generates the second selection signal LSB_L or thethird selection signal LSB_H to be used for sensing a lower bit inresponse to the higher data bit MSB_D. For example, if the higher databit MSB_D is ‘1’, the second selection signal LSB_L is generatedtherefrom. If the higher data bit MSB_D is ‘0’, the third selectionsignal LSB_H is generated therefrom. The second or third selectionsignal, LSB_L or LSB_H, is applied to the switching circuit 152. Duringthis, the sense amplifying circuit 120 detects a lower data bit, and thelower data bit detected is held in the data latch circuit 140 afterpassing through the data buffer 130.

The controller 154 provides control signals BLPRE, BLDIS, BIAS, ENMSB,ENBF, and PRST to the sense amplifying circuit 120, the data buffer 130,the data latch circuit 140, and the reference voltage selection circuit153 for the serial sensing operation. Timing features of the controlsignals supplied from the controller 154 are shown in FIGS. 3 and 4described as follows.

FIG. 3 is a timing diagram showing the states of various signals duringan operation of the NOR flash memory device illustrated in FIG. 2,illustrating the feature of the serial sensing operation to initialize adata line before sensing each of multiple data bits.

First, a bitline biasing signal BIAS is activated. While the bitlinebiasing signal BIAS is being active, the bitline discharging signalBLDIS is enabled. Subsequently, the bitline precharging signal BLPRE isapplied thereto, the output terminal SAO of the sense amplifying circuit120 is set to high level. During this, an output terminal of the databuffer 130, i.e., the data line DL, is in an unknown, or floating,state. Before sensing the higher data bit, the output terminal of thedata buffer 130 is initialized in response to the reset signal PRSTprovided from the controller 154. The reference selection circuit 153generates the first selection signal MSB_M to be used in detecting thehigher data bit in response to the higher-bit enabling signal ENMSB. Thesense amplifying circuit 120 then detects the higher data bit. The databuffer 130 buffers the higher data bit in response to the bufferenabling signals ENBF and nENBF, and the data latch circuit 140 holdsthe higher data bit buffered to the data line DL.

Next, before sensing the lower data bit, the output terminal of the databuffer 130 is initialized again in response to the reset signal PRSTprovided from the controller 154. The reference selection circuit 153generates the second or third selection signal, LSB_L or LSB_H, to beused in detecting the lower data bit in response to the higher data bitMSB_D. The sense amplifying circuit 120 then detects the lower data bit.The data buffer 130 buffers the lower data bit in response to the bufferenabling signals ENBF and nENBF, and the data latch circuit 140 holdsthe lower data bit buffered to the data line DL.

FIG. 4 is a timing diagram showing the states of various signals duringinitialization of a data line during a serial sensing operation in theNOR flash memory device.

Referring to FIG. 4, while sensing the higher data bit under activationof the first selection signal MSB_D, the output terminal DL of the databuffer 130 is initialized in response to the reset signal PRST providedfrom the controller 154. The data buffer 130 buffers the higher data bitin response to the buffer enabling signals ENBF and nENBF, and the datalatch circuit 140 holds the higher data bit buffered to the data lineDL. Next, while sensing the lower data bit under activation of thesecond or third selection signal LSB_L or LSB_H, the output terminal ofthe data buffer 130 is initialized again in response to the reset signalPRST provided from the controller 154. The data buffer 130 buffers thelower data bit in response to the buffer enabling signals ENBF andnENBF, and the data latch circuit 140 holds the lower data bit bufferedto the data line DL.

As stated above, the NOR flash memory device in accordance with thepresent invention initializes the output terminal of the data bufferbefore or while sensing each of the plural data bits by the senseamplifying circuit. Thus, it is capable of conducting a stabilizedserial sensing operation because the data line is conditioned with auniform level irrespective of the pattern of a data bit previouslysensed. In addition thereto, the serial sensing technique according tothe present invention is advantageous in assuring a higher sensingmargin than the conventional approach and in enhancing sensing speed,and in stabilizing the sensing operation.

While this invention has been particularly shown and described withreferences to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade herein without departing from the spirit and scope of the inventionas defined by the appended claims.

Accordingly, the NOR flash memory device of the present inventioninitializes the output terminal of the data buffer before sensing, orwhile sensing, each of the plural data bits by the sense amplifyingcircuit. Therefore, the present invention is effective in conducting astabilized serial sensing operation because the data line is conditionedto a uniform charge level irrespective of the pattern of a data bitpreviously sensed.

1. A method of sequentially sensing multiple data bits stored in amultilevel cell of a NOR flash memory device, the method comprising:initializing a data line and sensing a higher data bit; loading thesensed higher data bit on the data line and latching the loaded higherdata bit; initializing the data line and sensing a lower data bit inresponse to the latched higher data bit; and loading the sensed lowerdata bit on the data line and latching the loaded lower data bit.
 2. Themethod as set forth in claim 1, wherein the data line is initializedbefore sensing the higher data bit.
 3. The method as set forth in claim2, wherein the data line is initialized before sensing the lower databit.
 4. The method as set forth in claim 1, wherein the data line isinitialized while sensing the higher data bit.
 5. The method as setforth in claim 4, wherein the data line is initialized when beginning tosense the higher data bit.
 6. The method as set forth in claim 4,wherein the data line is initialized while sensing the lower data bit.7. The method as set forth in claim 6, wherein the data line isinitialized when beginning to sense the lower data bit.